2014 IEEE-EDS 纳米CMOS技术学术研讨会(WIMNACT 43),2014,11.28
作者: 发布日期:2014-11-28

by Prof. Steve S. Chung, NCTU Chair Professor/UMC Chair Professor, Chiao Tung University





    Moore's Law has driven CMOS devices scaling for several decades. The random phenomenon becomes increasingly important with the further scaling of CMOS technology. Two major sources of the variability will first be discussed, RDF (Random Dopant Fluctuation) and RTF (Random Trap Fluctuation). The former is induced by the process, while the later is induced by the devices after the electrical stress. For process-induced Vth variation, the major source of variability for conventional CMOS devices comes from the random dopant fluctuation (RDF) in the device channel. The theoretical basis from an experimental discrete dopant profiling technique will first be introduced to analyze the RDF effect. Then, for stress-induced Vth variation, the RTF will be introduced. In general, the trigate device structure has been able to suppress the RDF effect. However, the increasing RTF effect becomes critical to the development of trigate CMOS devices. More in-depth study of the Vth variation for devise after the electrical stress will be elucidated in this paper. The corner rounding, STI effect, series resistance effect in the trigate device will also be addressed. Moreover, more recent results to demonstrate the trap profiling with comprehensive RTN technique and its correlation to the device reliability will be demonstrated.

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